Access order to avoid inter-vector-conflicts in complex memory systems

The performance of a vector processor accessing vectors is strongly dependent on the conflicts produced in the memory subsystem. These conflicts delay the work of the functional units. The concurrent memory access of several vector streams causes inter-conflicts between the references of the different vector streams. In a memory system where several memory modules are mapped in every bus (complex memory system) the number of conflicts increases because the bus must be shared by vector streams. Conflicts named linked conflicts and complex conflicts decrease the performance of the steady-state phase in complex memory systems (CRAY X-MP). This paper proposes a method that allows a concurrent access to several vector streams reducing the average memory access time in vector processors with complex memory systems.